Digital counters are well-known electronic devices that provide an n-bit count that runs between 2.sup.n -1 and 0. For such a counter to function properly, the counter must be capable of accurately counting down from 2.sup.n -1 to zero or up from zero to 2.sup.n -1, depending on whether the counter is of the count-down or count-up variety, respectively. To properly test a counter, each of its counts must be verified. One past testing approach has been to clock the counter and then compare each count to an expected count generated by a reference counter. This approach incurs the disadvantage that a reference counter of equal length is required to generate a reference count for comparison purposes. The need for a reference counter increases the overhead of the circuit in the event that the reference counter is incorporated to accomplish Built-In Self-Testing.
Thus, there is a need for a technique for more efficiently testing a large counter.